adder tree
英 [ˈædə(r) triː]
美 [ˈædər triː]
网络 加法器树; 加法树
双语例句
- Circuits of asynchronous adder are proposed. An asynchronous multiplier using booth decode and based on Wallace tree architecture is designed.
给出了处理器中异步加法器的电路结构，设计了一个采用Booth译码wallacetree结构的异步乘法器。 - The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.
研究了并利用PE（处理单元）结构时序约束和加法树结构的加法阵列优化设计性能。 - In order to deal with the significant digits addition we designed three inputs adder tree, and give a simple performance discuss of this method.
针对有效数相加问题，本文提出了三输入加法树的设计方法，并就其性能作了简要的分析。 - A processing element array and an adder tree structure are used to improve the execution speed of SAD computation. The pipeline of the PE array and the adder tree is partitioned carefully in order to increase the work frequency.
本文结构由处理单元阵列和加法树组成核心计算结构，并对其流水线进行了细致地划分，提高了工作频率和运算速度。 - We proposed a dual field multiplier constructed from dual field adder and Wallace Tree. By this multiplier, dual field ECC is supported with small area and less energy assumption.
本文提出了采用双域加法器和wallacetree构造双域乘法器，从而支持了两种有限域的椭圆曲线密码算法，同时还具有面积小、功耗低的特点。